library ieee;
use ieee.std_logic_1164.all;

entity maindec_tb is
end maindec_tb;

architecture behav of maindec_tb is
    component maindec
        port(
        Op: in std_logic_vector(5 downto 0);
        MemToReg, MemWrite, Branch, AluSrc, RegDst, RegWrite, Jump: out std_logic;
        AluOp: out std_logic_vector(1 downto 0)
        );
    end component;

    signal OP_s: std_logic_vector(5 downto 0);
    signal MTR_s, MW_s, Br_s, AS_s, RD_s, RW_s, Jmp_s: std_logic;
    signal AO_s: std_logic_vector(1 downto 0);

begin
    MD0: maindec port map(OP_s, MTR_s, MW_s, Br_s, AS_s, RD_s, RW_s, Jmp_s, AO_s);

    process
    type input_array is array (natural range <>) of std_logic_vector(5 downto 0);
    type output_array is array (natural range <>) of std_logic_vector(8 downto 0);
    constant inPatterns: input_array :=
                                ("000000", "100011", "101011",
                                 "000100", "001000", "000010");
    constant outPatterns: output_array :=
                                ("000011010", "100101000", "010100000",
                                 "001000001", "000101000", "000000100");
    begin
        for i in inPatterns'range loop
            OP_s <= inPatterns(i);
            wait for 1 ns;
            assert MTR_s = outPatterns(i)(8);
            assert MW_s = outPatterns(i)(7);
            assert Br_s = outPatterns(i)(6);
            assert AS_s = outPatterns(i)(5);
            assert RD_s = outPatterns(i)(4);
            assert RW_s = outPatterns(i)(3);
            assert Jmp_s = outPatterns(i)(2);
            assert AO_s = outPatterns(i)(1 downto 0);
        end loop;
        wait;
    end process;
end behav;
